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Neeraj Paliwal

VP and General Manager

Rambus Security

Biography

20+ years of experience in building complex SoC products and leading global teams:

  • Deep technical expertise in semiconductor systems including hardware and software
  • Led 1000+ people global engineering team for 1B+ revenue business
  • Results-driven, people-oriented, and system-thinking leader
  • Application expertise in computing and security domains

Interests

  • Hardware Security
  • ASIC SoC Chip product development
  • EDA design methodology
  • deep learning hardware
  • AI hardware accelerator
  • semiconductor device and IP
  • embedded software systems
  • microprocessors
  • graphics and gaming processors
  • secure element
  • NFC
  • payment systems
  • secure OS hardening
  • encrypted communications

Education

  • Stanford Executive Program, Business/Leadership

    Stanford University

  • Masters Degree, Solid State Materials (Physics)

    Indian Institute of Technology, Delhi

Experience

 
 
 
 
 

Vice President and General Manager

Rambus Security

2018 – Present California
 
 
 
 
 

Founder and CEO

KRYPTOS Solutions Inc.

2015 – 2018 San Francisco
Kryptos developed an end to end secure military-grade mobile platform based upon Android AOSP. Responsible for all aspects of the startup, from starting business entity to architecture details. Primary focus on government and financial institutes. Completed IP transfer sale to customer in October 2017.
 
 
 
 
 

VP Engineering, Security & Connectivity (formerly Identification)

NXP Semiconductors

2011 – 2015 Hamburg, Germany
  • Responsible for the product development for 1Billion$+ revenue Identification business. Main focus on building an engineering organization that delivers products with the quality and speed required by Identification customers.
  • Led global engineering teams in the areas of Cryptography, RF/Contactless Technologies, Secure Element IC, Secure ASIC, NFC, Global Platform Java OS, and Mobile System.
 
 
 
 
 

VP, Central Engineering & NXP India Country Manager

NXP Semiconductors

2007 – 2011 Bangalore, India
  • Led central engineering teams in Netherlands, Germany, Belgium, UK, France, and India.
  • Built lean, efficient, and transparent central design engineering teams of 250+ engineers worldwide. This enabled NXP business lines to meet their time-to-market requirements.
  • Led NXP’s India operations, built 10 NXP labs at engineering universities across India.
 
 
 
 
 

Senior Engineering Manager, Design Methodology

IBM

2003 – 2007 Austin, TX
  • Started with IBM as an engineer in Chip Integration team for the first generation CELL processor chip (SONY PlayStation3). Led the final verification efforts for overall 1Billion+ transistors on CELL chip.
  • Led design tools and methodology team for IBM’s gaming processors supporting 600+ designers worldwide working on SONY Playstation3 and Microsoft XBOX360 processor development.
 
 
 
 
 

Senior Design Engineer

Intel Corporation

1999 – 2003 Austin, TX
  • Chip design methodology, physical design, and chip integration roles at Intel’s 32-bit Microprocessor and 64-bit Chipset Groups
  • Started as Design Methodology engineer in DuPont WA and within four years progressed to lead Design Floorplan for 32-bit Intel Microprocessor (Tejas) in Austin TX.
 
 
 
 
 

Senior Designer

Duet Technologies

1997 – 1999 Bellevue WA and Noida, India
  • Design and architecture of sub-micron standard cell IP libraries
 
 
 
 
 

Engineer

ITI Ltd.

1996 – 1997 Bangalore, India
  • Semiconductor Lithography Engineering on Ultratech Stepper for 1um process technology

Leadership Summary

Engineering executive with 20+ years of experience building complex products for top customers in security and computing domains (Government Secure Mobile KRYPTOS OS, Mobile OEMs Apple/Samsung Secure Payment System, SONY PlayStation3 GPU, Microsoft XBOX 360 GPU, and Intel Microprocessor CPU)

  • Led global teams of 1000+ engineers and 240+M$ R&D budget for NXP’s Security & Connectivity business
  • Led complex product portfolio of 90+ concurrent annual projects with 7 product lines and 1.5+B$ revenue
  • Led multiple 150M$+ customer design wins at top Mobile OEMs for NXP
  • Expert in leading to success on complex turn-around situations (NFC - Galaxy S4 loss to Galaxy S5 win)
  • Proven track record in motivating teams to push limits on product (power, performance, and area)
  • Results-driven, people-oriented, and system thinking approach to motivate staff to excellence
  • Proven track record in entering new applications (security in 2011) and leading to success within 3 years
  • Expert in building relationships, leading dialogues and negotiations with internal and external executives
  • Experience in media and industry engagements as speaker at conference, forums, and town-halls
  • Proven track record in building deep engagement across global teams (Gallup-score 4.04 to 4.31 in 3 years)
  • Straight forward ownership driven style to motivate team towards results (no politics, no BS, no CYA)
  • Strong interpersonal, communication, and coaching skills to build cohesive global teams
  • Diverse work experience in terms of:
    • Countries: Lived and led international teams in the United States, Europe, and Asia
    • Companies: Proven record of delivering complex products at NXP, IBM, Intel, and startups
    • Industries: Worked on Computing, Security, Gaming, Mobile, and Defense applications

Results

Consistent track record of building global teams and delivering top performance

  • KRYPTOS

    • 2017: Startup exit via Platform IP sale within three years of start (www.kryptos.us)
  • NXP

    • 2014: Apple iPhone 6 NFC design win via R&D transformation with 2X faster Time to Market
    • 2011: Elected Executive Board Member of the India Semiconductor Association (1st for NXP)
  • IBM

    • 2005: Recognized as high potential talent for NextGen program (Only 140 picked out of 300,000+ IBMers)
    • 2005: Outstanding Technical Achievement (OTA) award on Microsoft’s XBOX 360 project
  • Intel

    • 2001: Divisional Recognition Award (DRA) for breakthrough design methodology (5X improvement - time)
    • 2000: Development leadership pioneer award for Intel’s 64-bit server chipset design (Intel 82870 chipset)
  • Duet

    • 1998: Outstanding engineer award for building 10% faster Standard Cell Library in NEC 0.18um technology
  • Academic

    • 1996: Graduated top of the class at IIT Delhi Masters in Solid State Materials program
    • 1995: Senior research fellowship award to start PhD (Council of Scientific and Industrial Research, India)
    • 1994: All India Rank 62 in Physics at GATE examination - Awarded scholarship at IIT Delhi
    • 1994: Graduated Master of Science Physics University Valedictorian (Gold Medalist)
    • 1989-1992: National Merit Scholarship for High School academic performance at UP Board, India

Media Mentions

Blog

On this blog, I write about four interest areas: (1) Semiconductors Technology, Hardware, Software & Systems (2) It’s applications in security, payments, automotive, and deep learning (3) Leadership, as it relates to transforming team to deliver results (4) Journey, specifically a peak-through learnings in my life

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